(1) Field of the Invention
This invention relates to a new reversed flash memory device. This new reversed flash memory device has improved electrical performance, yield and reliability due to better control of the dielectric interfaces within the reversed flash memory device. This better control is achieved by first creating the poly 2 control gate in the silicon substrate.
(2) Description of the Prior Art
The flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) device is so named because the contents of all the memory array cells can be erased simultaneously through the use of an electrical erase signal. The flash refers to the fact that the cells can be erased much more rapidly (1 or 2 seconds, compared to the 20 minutes required to erase a UV-EPROM). Large size memories are at this time available that offer a byte-by-byte erase capability.
The erasing mechanism in flash EEPROM's is Fowler-Nordheim tunneling off of the floating gate to drain region. Programming of the floating gates is carried out in most flash cells by hot-electron injection into the gate. Floating gate EEPROM's incorporate a separate select transistor in each cell to allow for individual byte erasure while flash memories forego the select transistor in order to obtain bulk erasure capabilities.
Most present day flash-EEPROM cells use a double-poly structure. The upper poly forms the control gate or the word lines of the structure, while the lower poly is the floating gate. The gate oxide is approximately 10 nm. thick (physical thickness), the interpoly dielectric is an oxide/nitride/oxide composite film approximately 20 nm. thick (physical thickness). Part of the structure can be a special, software controlled erase gate which is instrumental in assuring that the floating gate is not over-erased.
Flash EEPROMS can be seen to combine the advantages of UV-erasable EPROM's and floating gate EEPROM's. They offer the high density, small die size, lower cost and hot electron writability of EPROM's, together with the easy erasability, on-board re-programmability and electron-tunneling erasure features of EEPROM's.
The reliability of the flash memory device is often dependent on the interfacial conditions between the tunneling oxide and poly 1, as well as between the interpoly dielectric and the adjacent layers. For example, the inherent surface roughness of the deposited poly 1 often causes a rough, edgy surface upon which to grow/deposit the interpoly dielectric.
The poly 1 layer for the floating gate is usually deposited first (by implant doping). This prior-art process methodology causes the existence of non-uniform regions of high dielectric field stress in the interpoly dielectric, which accelerates the time-dependent breakdown of the interpoly dielectric. A similar assessment can be made about any dielectric weakness in the thin tunneling dielectric layer constructed between the source and drain of any transistor used for flash memory devices.
FIG. 1 shows the Prior Art construction of a flash memory cell device. The control gate 12 is labeled poly 2, the floating gate 11 is labeled poly 1. Imperfect interfaces caused by poly 1 surface roughness severely impair the integrity of the device dielectrics during plasma chamber electrode charging and/or device stress testing of the electrical parameters. The source 17 and drain 18 are located in the single silicon substrate 19, the interpoly layer 14 is seen between poly 1 and poly 2. The thin tunneling layer 16 is constructed on the single crystal substrate above the source and drain. The connecting tab to the poly 2 (the control gate) is made with the tungsten silicide layer 13 and the poly cap 15.
FIG. 2 shows a physical and mathematical model of the rough surface created by LPCVD of poly 1 layer 11 (FIG. 1), which is characteristic of the conventional (Prior Art) flash memory device structure. The mathematical model is based on the equation E.sub.edge /E.sub.plane =((1+(r/T.sub.ono)) )/(r/T.sub.ono). The electric field increases with decreasing distance between two charge points. The equation is a ratio relating the E-field at the convex edge 32 to that in the planar edge face 31, where r is the radius 36 of the convex edge 32 and T.sub.ONO is the period/distance between roughness cycles within the interpoly layer 33 of ONO. Layer 34 is the layer of poly 1 (the Prior Art floating gate), layer 35 is the layer poly 2 (the Prior Art control gate). The equation demonstrates the effect of sharp (small "r") imperfections in the semiconductor surface. A small radius "r" makes the ration r/T.sub.ONO small, since the ratio E.sub.edge /E.sub.plane is inversely proportional to the ratio r/T.sub.ONO the small "r" (sharp surface irregularities) results in a large value for the ratio E.sub.edge /E.sub.plane. This indicates that surface irregularities in the surface of the poly 1 layer 32 result in creating points of high electric field concentration in the interpoly ONO layer 33. Surface irregularities and therefore points of high electric field concentration are further emphasized when subjecting the surface to plasma charging or electrical stressing. The result is a severe performance degradation of the Prior Art flash memory device.
U.S. Pat. No. 5,479,368 to Keshtbod shows a flash cell with an interpoly dielectric formed on a substrate and a vertically floating gate.
U.S. Pat. No. 4,957,877 to Tam et al shows a method for forming a flash dual cell with doped regions under a finger of a floating gate.
U.S. Pat. No. 5,587,332 to Chang et al. shows a flash memory cell with polysilicon control gate on top of the interpoly dielectric layer, and the source/drain implanted in the silicon substrate, which is the conventional stacking structure.